1. Field of Invention
The present invention relates to the decoding processing of bitstreams encoded in accordance with an arithmetic-encoding system in image compression such as ITU-T Rec. H.264|ISO/EC 14496-10 AVC by JVT.)
2. Description of the Related Art
In recent image data compression, standards such as International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC) by Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG are being set up to provide higher compression. The standard is often called H.264/MPEG4-AVC in short. In the following description, the standard is simply referred to as H.264.
In the H.264 standard, an arithmetic-encoding system is used to encode bitstreams. Arithmetic encoding converts multivalued signals into binary signals. Therefore, the binary signals are converted into the multivalued signals to decode the bitstreams. At this time, a Context-based Adaptive Binary Arithmetic Coding system (hereinafter called a “CABAC”) is used in the conversion.
In the CABAC, there is provided a context-calculating unit operable to calculate the probability of symbols, and arithmetic-decoding calculation is performed based on the calculated probability from the context-calculating unit. In bitstreams having experienced the arithmetic-decoding calculation, the binary signals are converted into the multivalued signals.
At this time, the arithmetic-decoding calculation and context calculation are designed to treat incoming bitstreams serially, and the ultimately multivalued data is generated in dependence upon processing speeds of the arithmetic-decoding calculation.
Cited Reference No. 1 (published Japanese Patent Application Laid-Open No. 2004-136261) discloses the decoding of bitstreams in accordance with the arithmetic-decoding system. According to arithmetic decoding as taught by the cited Reference No. 1, when a bit amount of each of incoming bitstreams is greater than a processing amount of the arithmetic decoding, then the bitstreams are treated as an error.
Another cited Reference No. 2 (US2004/0085233A1) discloses an art operable to divide decoding processing into two stages using a memory. According to the cited Reference No. 2, the memory temporarily stores incoming bitstreams. A transcoder unit reads the bitstreams out of the memory to decode and then encode the bitstreams, and transfers the encoded bitstreams back into the memory. The bitstreams taken out of the memory are re-decoded to display images.
However, according to the decoding-processing unit as disclosed by the cited Reference No. 1, both of the arithmetic-decoding calculation and the context calculation can treat the bitstreams only serially. Meanwhile, the multivalued conversion is followed by image display based on the decoded data. At this time, images must be displayed in real time, and required data amounts must be decoded within a predetermined period of time.
For example, for a high-vision (hereinafter called a “ED-TV”) image, data consisting of 1920 pixels-by-1088 lines must be decoded at the speed of 1/30 seconds, i.e., 33.3 msec. It follows that time required to decode a micro block (hereinafter called a “MB”) is 33.3/8160 or approximately 4085 nsec.
As specified by the H.264 standard, the maximum bit amount for a MB has the value of 3200-bit. According to the maximum bit amount, one-bit must be decoded at the speed of 4085/3200 or approximately 1.27 nsec to decode a HD-TV image. The speed corresponds to a clock frequency of some 784 MHz.
Such high clock signals as high as 784 MWH have a problem of severe difficulties in designing the decoding-processing apparatus.
According to the cited Reference No. 1, data that remain to be decoded because of a delay in decoding processing are handled as errors. However, an increase in amount of data treated as errors brings about another problem in that proportionally non-uniform and disturbed images are reproduced.
According to the cited Reference No. 2, the memory compensates a difference between data-processing speed required for image reproduction and data-processing speed in the arithmetic decoding. However, the cited Reference No. 2 fails to show a specific construction operable to synchronize the bitstreams between the transcoder unit and a decoding unit at a last stage. This causes problems that a failure in processing of the bitstreams, errors in decoding, and so on are likely to occur when the memory absorbs the difference in processing speed. Furthermore, the fact that the data at first decoded is re-encoded to decode the re-encoded data involves yet further problems of complex processing, prolonged time lapse between the entry of the bitstreams and the ultimate display of images, and consequential poorness in usability.
In view of the above, the present invention provides a decoding-processing apparatus and method operable to perform both arithmetic decoding calculation and multivalued calculation at clock speeds that facilitate the design of the decoding-processing apparatus, while displaying images in real time.